Impact of Interlayer and Ferroelectric Materials on Charge Trapping During Endurance Fatigue of FeFET With TiN/Hf_<i>x</i>Zr_1-<i>x</i>O₂/Interlayer/Si (MFIS) Gate Structure

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during endurance fatigue Si field effect transistor (FeFET) with TiN/HfxZr1-xO2/ interlayer/Si (MFIS) gate-stack. have fabricated FeFET devices (SiO2 or SiON) HfxZr1-xO2 ( ${x} =0.75$ , 0.6, 0.5) directly extracted fatigue. find that: 1) under same equivalent oxide thickness (EOT) condition, increase dielectric constant interlayer suppresses improves characteristics; 2) is experimentally verified to be origin fatigue; 3) as spontaneous polarization notation="LaTeX">${P}_{\text {s}}{)}$ decreases from notation="LaTeX">$25.9~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.5Zr0.5O2) notation="LaTeX">$20.3~ (Hf0.6Zr0.4O2), behavior decreases, resulting in slow degradation rate memory window (MW) program/erase cycling; addition, when {s}}$ further notation="LaTeX">$8.1~ }\text{C}$ (Hf0.75Zr0.25O2), initial MW nearly disappears (only &#x007E;0.02 V). Thus, reduction could improve characteristics. On contrary, it can also reduce MW. Our work helps design MFIS gate-stack